This invention relates generally to delay circuits for delaying an input signal for a predetermined time and, more particularly, to a delay circuit which is stable against voltage and temperature changes.
A conventional delay circuit such as described in U.S. Pat. No. 4,496,861 is shown in FIG. 7. This delay circuit includes an oscillator 14 for generating a continuous clock signal A, a frequency divider 1 for shaping the clock signal A into a square wave basic clock signal 2, pulse generators 3-6 made of exclusive OR circuit, voltage controlled delay elements (VCD) 7-10, a sample hold circuit 11 for holding an output of the N-th pulse generator 6, and a low pass filter 12 for generating a control voltage 13 based on a signal from the sample hold circuit 11.
In operation, the basic clock signal 2 from the frequency divider 1 is delayed for a predetermined period of time by the first VCD 7 and made into a pulse CP.sub.0 with the width equal to the delay by the first pulse generator 3. The delayed clock signal from the first VCD 7 is put into the second VCD 8 for a predetermined delay and made into a pulse CP.sub.1 with the width equal to twice the delay time by the second pulse generator 4. Similarly, the third VCD 9 and the pulse generator 5 generate a pulse CP.sub.2 with the width equal to three times the delay time. In this way, the N-th VCD 10 and the N-th pulse generator 6 generates a pulse CP.sub.N with the width equal to N times the delay time. This output pulse CP.sub.N is held by the sample hold circuit 11 and then converted by the low pass filter 12 into a voltage which is applied to the VCD 7-10 as a control voltage 13.
In the above delay circuit, however, the delay pulses CP.sub.0 -CP.sub.N are not generated unless a clock signal is supplied continuously. As a result, it has been impossible to provide a delayed output of a given pulse input.
FIG. 8 shows a delay circuit which is capable of providing a delay output of a given pulse input. This delay circuit includes buffers 21a-21n in the form of an emitter coupled logic (ECL), resistors 22a-22n, capacitors 23a-23n, output buffers 24a-24n, and a data selector 25 responsive to a selection signal 26 from a control unit (not shown) to select signals from the output buffer 24. The respective ECL buffers 21 are connected in series via each resistor 22. The respective output buffers 24 are connected between the respective ECL buffers 21 and the data selector 25. An end of each capacitor 23 is connected to an output of each resistor 22. The data selector 25 consists of a decoder 25a responsive to the selection signal 26 to output a signal at a predetermined signal line and a switching circuit 25b responsive to a signal from the decoder 25a to output a delayed signal from the output buffer 24.
In operation, a pulse signal B input to the ECL buffer 21a is put into an integration circuit consisting of the resistor 22a and the capacitor 23a. The output is applied to the next ECL buffer 21b with a delay determined by the time constant of the resistor 22a and the capacitor 23a. In general, the delay of the ECL buffers 21a-21n is smaller than the time constant so that the values of the resistor 22 and the capacitor 23 should be sufficiently precise to provide the delay time. The respective delay signals thus output from the ECL buffers 21a-21n via the output buffers 24a-24n are put into the data selector 25 to provide a delay signal C selected in response to a selection signal 26 which is set according to a desired delay time.
In order to set accurately a very short delay time, such as in order of nanoseconds, in the conventional delay circuit, it has been necessary to machine by laser trimming techniques the IC pattern of a finished semiconductor ship so as to adjust the respective values of the resistors 22 and capacitors 23 for providing an accurate CR time constant. In addition, since the ECL buffers 21 are used to control the delay output, it is necessary for ordinary logic circuits to provide another power source, such as a negative power source or level shifter, thus making the fabrication of an integrated circuit difficult.
FIG. 9 shows a simple circuit which consists of CMOS inverters 28a-28n in the form of a cascade connection to provide a delay time in nanoseconds. However, the CMOS inverters 28 varies with voltage and temperature changes, thus changing the delay time, so that it is necessary to provide a correction circuit. In addition, the characteristics of integrated circuits change from lot to lot in production, thus requiring troublesome adjustment of the finished products.